1. Field
The present invention is related to aligning a sequencer clock and a buffer clock before transferring data to a buffer.
2. Related Art
Typically, logic devices are under control of different clocks. Data cannot be efficiently transferred from a first logic device to a second logic device if the clocks are not aligned or skewed. Thus, to properly transfer or write the data from the first logic device to the second logic device, the clocks need to be aligned. One way to align clocks before transferring or writing is to use a deskewing phase lock loop that receives both clock signals, and aligns a signal from a data receiving device with respect to a data sending device. However, the deskewing phase lock loop typically occupies a lot of real estate on a chip. With chips being required to include more and more devices, this additional space becomes costly.
Therefore, what is needed is a system and method that would allow for proper aligning of clock signals of devices sharing data using a device that takes up less real estate on a chip than a deskewing phase lock loop.
The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers may indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number may identify the drawing in which the reference number first appears.